Accommodating workload diversity in chip multiprocessors via

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Complexity is reduced by designing and verifying a single, relatively simple core, and then replicating it.

In a further embodiment, the method of these teachings for enabling executing code collectively at a number of processing units includes reconfigurably linking one processor unit to another processor unit and fetching and providing instructions to be executed collectively by the processor units.Hence, while ACMPs may deliver increased performance on sequential codes, they may do so at the expense of parallel performance, requiring a high level of software sophistication to maximize their potential.Instead of trying to find the right design trade-off between complex and simple cores (as ACMPs do), there is a need for a CMP that provides the flexibility to dynamically synthesize the right mix of simple and complex cores based on application requirements.The exemplary embodiment presented hereinbelow start from a CMP substrate with a homogeneous set of small cores.The embodiment maximizes the core count to exploit high levels of thread level parallelism (TLP), and has the modularity advantages of fine-grain CMPs.

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